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Floating-point and multibit-increment digital-differential-analyser structures

Floating-point and multibit-increment digital-differential-analyser structures

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The possibilities of establishing digital-differential-analyser structures possessing both high solution accuracies and automatic scaling are examined. Two such structures are given, together with their performance characteristics. The second of these, the dynamic-increment digital differential analyser, introduces the concept of a digital differential analyser with the length of its incremental output dynamically varying during the solution process.

References

    1. 1)
      • Hyatt, G.P., Ohlberg, R.N.: `Electrically alterable digital differential analyzer', Proceedings of the AFIPS Conference, SJCC, 1968.
    2. 2)
      • Gaines, B.R.: `A modular programmed DDA for real-time computation', Proceedings of the IFIP Congress, 1968, Edinburgh.
    3. 3)
      • R.B. McGhee , R.N. Nilsen . The extended resolution digital differential analyzer: A new computing structure for solving differential equations. IEEE Trans. , 1 - 9
    4. 4)
      • Elshoff, J.L., Hulina, P.T.: `The binary floating point digital differential analyzer', Proceedings of the AFIPS Conference, SJCC, 1970.
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