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Level-shift compensation in m.o.s. bucket-brigade circuits operated in an analogue mode

Level-shift compensation in m.o.s. bucket-brigade circuits operated in an analogue mode

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As a result of net loss (or gain) of charge to the substrate, the signal component at the output of a bucket-brigade circuit is subject to a direct-voltage shift which reduces the dynamic range of the device. Compensation for such level-shifting (of either polarity) can be provided by means of single additional m.o.s. devices placed at suitable intervals along the delay line.

Inspec keywords: metal-insulator-semiconductor devices; signal processing; delay lines

Other keywords: level shift compensation; gain; MOS; delay lines; signal processing; analogue mode; metal insulator semiconductor devices; substrate

Subjects: Other analogue circuits

References

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      • W.E. Engeler , J.J. Tiemann , R.D. Baertsch . Surface charge transport in silicon. J. Appl. Phys. , 469 - 471
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      • Boonstra, L., Sangster, F.L.J.: `Progress on bucket-brigade charge-transfer devices', Presented at the IEEE international solid-state circuits conference, February 1972, Philadelphia, Pa..
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      • C.N. Berglund . Analog performance limitations of charge transfer dynamic shift registers. IEEE J. Solid-State Circuits , 391 - 394
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      • J.I. Brugler , P.G.A. Jespers . Charge pumping in MOS devices. IEEE Trans. , 297 - 302
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      • W.S. Boyle , G.E. Smith . Charge-coupled semiconductor devices. Bell Syst. Tech. J. , 587 - 593
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      • Butler, W.J., Puckette, C.M., Barron, M.B., Kurz, B.: `Analog operating characteristics of bucket-brigade delay lines', Presented at the IEEE international solid-state circuits conference, February 1972, Philadelphia, Pa..
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Erratum: Level-shift compensation in m.o.s. bucket-brigade circuits operated in an analogue mode
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