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Multiplier–divider cellular array

Multiplier–divider cellular array

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A single array performing multiplication or division of two binary numbers is proposed. Implemented with the new t.t.l. 4-bit integrated circuits, it performs these two operations on 16-bit numbers in 640 and 890 ns, respectively.

References

    1. 1)
      • J.C. Hoffman , B. Lacaze , P. Csillag . Multiplieur paralléle à circuits logiques itératifs. Electron. Lett.
    2. 2)
      • R. De Mori . Suggestions for an i.c. fast parallel multiplier. Electron. Lett. , 50 - 51
    3. 3)
      • K.J. Dean . Iterative arrays of logical circuits for performing arithmetic. Electron. Engng. , 694 - 697
    4. 4)
      • H.H. Guild . Some cellular logic arrays for non-restoring binary division. Radio & Electron. Engr. , 345 - 348
    5. 5)
      • K.J. Dean . Some applications of cellular logic arithmetic arrays. Radio & Electron. Engr. , 225 - 227
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