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Sensitivity performance of threshold-logic gates using Chow parameters

Sensitivity performance of threshold-logic gates using Chow parameters

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Existing analyses of the sensitivity of threshold-logic gates to input voltage and component tolerances are, in general, complex. It is here shown that the sensitivity performance of practical gate realisations may be related very simply to the Chow parameters of the gate.

References

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      • M.L. Dertouzos . (1965) Threshold logic: a synthesis approach, Research monograph 32.
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      • C.L. Sheng . (1969) , Threshold logic.
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      • P.E. Wood . A note on threshold device error analysis. IEEE Trans. , 403 - 405
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      • P.M. Lewis , C.L. Coates . Realization of logic functions by a network of threshold components of specified sensitivity. IEEE Trans. , 443 - 454
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      • D.R. Haring . A technique for improving the reliability of certain classes of threshold functions. IEEE Trans. , 997 - 998
    7. 7)
      • Amodei, J.J., Hampel, D., Mayhew, T.R., Winder, R.O.: `An integrated threshold gate', Digest of international solid-state circuits conference, 1967, New York, p. 114–115.
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