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Fast versatile binary comparator array

Fast versatile binary comparator array

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© The Institution of Electrical Engineers
Published

A 1-dimensional cascaded structure is normally employed with binary comparators operating in the parallel mode. An assignment of cell output states is proposed which enables a faster 2-dimensional array to be formed. An optional facility for detecting inputs of zero value may be simply incorporated in the design.

Inspec keywords: logic design; cellular arrays; comparators (circuits)

Other keywords: cellular array; inputs of zero value detecting facility; logic design; two dimensional array; fast versatile binary comparator array; parallel mode

Subjects: Logic design methods

References

    1. 1)
      • F.C. Hennie . (1961) , Iterative arrays of logical circuits.
    2. 2)
      • D. Zissos , G.W. Copperwhite . (1968) , Logical design manual.
    3. 3)
      • Linford, J.: `Error detection and correction using exclusive-OR gates and parity trees', AN-496, Application note, , Motorola Semiconductor Products.
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