access icon free High-performance and single event double-upset-immune latch design

This Letter proposes a single event double-upset (SEDU)-fully-tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area-power-delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.

Inspec keywords: MOSFET; radiation hardening (electronics); CMOS integrated circuits; CMOS logic circuits; flip-flops; logic design

Other keywords: SEDU; single event double-upset-fully-tolerant latch; recently reported latches; NMOS transistors; single event double-upset-immune latch design; 84.56% area-power-delay product saving; PMOS transistors; interlocked branch circuits

Subjects: Digital circuit design, modelling and testing; CMOS integrated circuits; Logic circuits; Insulated gate field effect transistors; Radiation effects (semiconductor technology); Logic and switching circuits

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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2020.1823
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