Error-compensated time integrator in 28-nm CMOS technology
A time-difference integrator is proposed to compensate for the time error caused by leakage current in gated delay-buffer cells. The proposed time integrator, consisting of two back-to-back connected time-difference adders, which are composed of two gated delay-buffer cells. The input time signals and accumulated output are periodically swapped into the time adder to neutralise the timing offset. Implemented in a 28-nm CMOS process, the time integrator achieves a gain of 27.39 dB with a 317 kHz 30 ps peak-to-peak sinusoidal input, and consumes 110.3 μW with a 50 MHz sampling rate from a 0.9 V supply.
