access icon free Bandpass ΔΣ ADC using pipelined SAR ADC

This Letter proposes a second-order bandpass ΔΣ ADC using a pipelined successive-approximation-register (SAR) ADC as an internal quantiser. The second-order bandpass noise-shaping is achieved by utilising the residue signal after SAR conversion and inherent delay existing in a pipelined structure. The proposed ADC can show very high resolution even with low-order noise-shaping and low oversampling ratio. Also, it shows good energy efficiency and a high sampling rate due to the use of a pipelined SAR ADC as a quantiser.

Inspec keywords: delta-sigma modulation; analogue-digital conversion; quantisation (signal)

Other keywords: energy efficiency; high sampling rate; second-order bandpass ΔΣ ADC; low oversampling ratio; inherent delay; residue signal; second-order bandpass noise-shaping; pipelined successive-approximation-register ADC; internal quantiser; pipelined structure; low-order noise-shaping; pipelined SAR ADC; SAR conversion

Subjects: A/D and D/A convertors; A/D and D/A convertors

References

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      • 1. Schreier, R., Temes, G.C.: ‘Understanding delta Sigma converters’ (Wiley, New York, NY, USA, 2005).
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      • 3. Yang, X., Lee, H.: ‘Design of a 6th-order continuous-time bandpass ΔΣ modulator with 250 MHz IF, 25 MHz bandwidth, and over 75 dB SNDR’. IEEE Int. Symp. on Circuits and Systems (ISCAS), Florence, Italy, May 2016, pp. 15.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2020.0314
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