Fast and exact multiple-input unary-to-binary multiplier with variable precision for stochastic computing
Stochastic computing offers an area-efficient solution for power-greedy computations in error-resilient applications such as image processing. However, stochastic computing produces only approximated results and suffers from long latency especially for multiplication. The authors present a multiplier design technique for stochastic computing which guarantees exact output and has latency in the order of 2 N (N = input precision), utilising the counter for unary-to-binary conversion. Compared to state-of-the-art deterministic methods the proposed design is faster by a factor of 2 N . Besides, the area of proposed design scales up in proportion to N instead of N 2, as opposed to conventional binary multipliers. The design technique can be further extended for multiple inputs and parallel computing, Extensive mathematical analysis and simulation results are presented for each variation throughout this Letter.
