References

• 1. 1)
     • 5. Verbruggen, B., Iriguchi, M., de la Guia Solaz, M., et al: ‘A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28 nm digital CMOS’. IEEE Symp. on VLSI Circuits, Kyoto, Japan, June 2013, pp. C268–C269.
  2. 2)
     • 4. Zhou, Y., Xu, B., Chiu, Y.: ‘A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector’, IEEE J. Solid-State Circuits, 2015, 50, (4), pp. 920–931 (doi: 10.1109/JSSC.2014.2384025).
  3. 3)
     • 6. Devarajan, S., Singer, L., Kelly, D., et al: ‘A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology’, IEEE J. Solid-State Circuits, 2017, 52, (12), pp. 3204–3218 (doi: 10.1109/JSSC.2017.2747758).
  4. 4)
     • 4. Wang, P., Sun, J., Wu, J.: ‘Dither-based background calibration of capacitor mismatches and gain error in pipelined noise shaping successive approximation register ADCs’, Electron. Lett., 2019, 55, (18), pp. 984–986 (doi: 10.1049/el.2019.0872).
  5. 5)
     • 3. Siragusa, E., Galton, I.: ‘Gain error correction technique for pipelined analogue-to-digital converters’, Electron. Lett., 2000, 36, (7), pp. 617–618 (doi: 10.1049/el:20000501).
  6. 6)
     • 8. Hong, H., Kim, W., Kang, H., et al: ‘A decision-error-tolerant 45 nm CMOS 7b 1 GS/s nonbinary 2b/cycle SAR ADC’, IEEE J. Solid-State Circuits, 2015, 50, (2), pp. 543–555 (doi: 10.1109/JSSC.2014.2364833).
  7. 7)
     • 1. Shu, Y.-S., Song, B.-S.: ‘A 15-bit linear 20-MS/s pipelined ADC digitally calibrated with signal-dependent dithering’, IEEE J. Solid-State Circuits, 2008, 43, (2), pp. 342–350 (doi: 10.1109/JSSC.2007.914260).
  8. 8)
     • 7. Sehgal, R., Goes, F., Bult, K.: ‘A 13-mW 64-dB SNDR 280-MS/s pipelined ADC using linearized integrating amplifiers’, IEEE J. Solid-State Circuits, 2018, 53, (7), pp. 1878–1888 (doi: 10.1109/JSSC.2018.2815654).