access icon free Hybrid low-k spacer scheme for advanced FinFET technology parasitic capacitance reduction

© The Institution of Engineering and Technology
Received 12/12/2019, Published 03/03/2020

Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable low-power and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1–5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C OV) and 3% reduction in ring oscillator effective capacitance (C EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V BD) and leakage current (I LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.

Inspec keywords: low-k dielectric thin films; leakage currents; semiconductor device breakdown; silicon compounds; permittivity; semiconductor device reliability; MOSFET

Other keywords: P/NFET overlap capacitance; SiOCN; integrated FinFET technology platform; low-k materials; low-dielectric constant material; size 7.0 nm; hybrid low-k spacer scheme; parasitic capacitance reduction; reliability characterisation; gate electrode; structural integrity; leakage current; FinFET gate sidewall spacer; dielectric breakdown voltage; advanced FinFET technology; dielectric properties; silicon oxycarbonnitride; ring oscillator effective capacitance; manufacturing process; deposition process

Subjects: Insulated gate field effect transistors; Reliability; Dielectric materials and properties

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