access icon free Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture

A voltage-mode pulse-amplitude modulation 4 (PAM4) driver with differential ternary R-2R DAC architecture is described. The differential ternary R-2R DAC provides three voltage levels with one R-2R branch, whereas the conventional one provides only two. Therefore, much less R-2R branches are required for a given number of output voltage levels. One of the three voltage levels is realised by simply short circuiting a differential input pair, saving power consumption. Implemented in 65 nm CMOS technology, the voltage-mode PAM4 driver occupies 0.073 mm2 active silicon area and consumes 1.97 mW/Gbit/s from 1.0 V supply at 10 Gbit/s.

Inspec keywords: CMOS integrated circuits; low-power electronics; digital-analogue conversion; driver circuits; pulse amplitude modulation

Other keywords: 2 active silicon area; R-2R branch; voltage-mode pulse-amplitude modulation 4 driver; voltage-mode PAM4 driver; size 65.0 nm; bit rate 10.0 Gbit/s; voltage 1.0 V; differential ternary R-2R DAC architecture; differential input pair; CMOS technology; output voltage levels; power consumption

Subjects: A/D and D/A convertors; Power electronics, supply and supervisory circuits; CMOS integrated circuits

References

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      • 3. Nazemi, A., Hu, K., Catli, B., et al: ‘A 36 Gb/s PAM4 transmitter using an 8b 18 GS/s DAC in 28 nm CMOS’. IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, USA, February 2015, pp. 5859.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2019.3863
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