access icon free High-efficient superblock flash translation layer for NAND flash controller

Flash controller is the core hardware embedded in today's mobile device storage, and the flash translation layer (FTL) is the key system of controller. This Letter proposes a high-efficient superblock FTL (HSPB) to satisfy the demand of large media files and application files storage, which implements the cross-block sequential writing strategy and the shared cached mapping table scheme. Test results show that HSPB reduces the time and power consumption by 7–30% in seq/random write and gains up to 60% improvement in sequential/random read compared to other FTLs.

Inspec keywords: NAND circuits; storage management; flash memories; cache storage

Other keywords: shared cached mapping table scheme; cross-block sequential writing strategy; high-efficient superblock FTL; media files; core hardware; mobile device storage; HSPB; application files storage; NAND flash controller; high-efficient superblock flash translation layer

Subjects: Semiconductor storage; File organisation; Logic and switching circuits; Logic circuits; Microprocessor chips; Performance evaluation and testing; Memory circuits

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2019.3526
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