A new uniform shallow trenches termination (ST²) with field plate for high-voltage VDMOS transistor is proposed in this Letter. In ST² structure, the electric field near the source is decreased and the depletion region is extended by the field plate, besides, many electric field peaks are introduced in shallow trenches under the field plate and the average electric field strength is increased, both improve the characteristic of the breakdown voltage (BV). Simulation results show the BV of ST² VDMOS is 706 V with a termination length L _d = 132 μm, which reaches 97% of that of the parallel-plane junction, and the influence of the edge curvature effect is almost entirely eliminated. The ST² structure is compatible with conventional CMOS process with only one additional mask and its fabrication is low-cost.

References

1. 1)
  - 10. Qian, Q., Sun, W., Zhu, J., et al: ‘A novel charge-imbalance termination for trench superjunction VDMOS’, Electron Device Lett., 2010, 31, (12), pp. 1434–1436 (doi: 10.1109/LED.2010.2076406).
2. 2)
  - 8. Oh, J.K., Ha, M.W., Han, M.K., et al: ‘A new junction termination method employing shallow trenches filled with oxide’, Electron Device Lett., 2004, 25, (1), pp. 16–18 (doi: 10.1109/LED.2003.821599).
3. 3)
  - 9. Duan, B., Yang, Y., Zhang, B.: ‘High voltage REBULF LDMOS with N+ buried layer’, Solid State Electron., 2010, 54, (7), pp. 685–688 (doi: 10.1016/j.sse.2010.03.003).
4. 4)
  - 2. Temple, V.A.K., Tantraporn, W.: ‘Junction termination extension for near-ideal breakdown voltage in p-n junctions’, Trans. Electron Devices, 1986, 33, (10), pp. 1601–1608 (doi: 10.1109/T-ED.1986.22713).
5. 5)
  - 12. Bose, J.V.S.C., De Souza, M.M., Narayanan, E.M.S., et al: ‘Influence of a shallow p + offset region on a novel edge termination technique using lightly doped p-rings’. CAS '99 Proceedings. 1999 International Semiconductor Conference, Sinaia, Romania, October 1999, pp. 63–66.
6. 6)
  - 5. Yang, K., Guo, Y., Pan, D.Z., et al ‘A novel variation of lateral doping technique in SOI LDMOS with circular layout’, Trans. Electron Devices, 2018, 65, (4), pp. 1447–1452 (doi: 10.1109/TED.2018.2808193).
7. 7)
  - 13. Cheng, J., Chen, X.: ‘New planar junction edge termination technique using OPTVLD with a buried layer’, Trans. Electron Devices, 2013, 60, (7), pp. 2428–2431 (doi: 10.1109/TED.2013.2264342).
8. 8)
  - 6. Ronsisvalle, C., Enea, V.: ‘Improvement of high-voltage junction termination extension (JTE) by an optimized profile of lateral doping (VLD)’, Microelectron. Reliab., 2010, 50, (9–11), pp. 1773–1777 (doi: 10.1016/j.microrel.2010.07.078).
9. 9)
  - 11. Seto, K., Kamibaba, R., Tsukuda, M., et al: ‘Universal trench edge termination design’. Proc. Int. Symp. Power Semiconductor Devices ICs, Bruges, Belgium, June 2012, pp. 161–164.
10. 10)
  - 3. Niwa, H., Suda, J., Kimoto, T.: ‘21.7 kV 4h-SiC Pin diode with a space-modulated junction termination extension’, Appl. Phys. Express, 2012, 5, (6), pp. 1–3 (doi: 10.1143/APEX.5.064001).
11. 11)
  - 9. Lin, J.L., Wen, L.W.: ‘Design, simulation, and fabrication of metal-oxide-semiconductor field-effect transistor (MOSFET) with new termination structure’, Trans. Electron Devices, 2012, 59, (12), pp. 3179–3185 (doi: 10.1109/TED.2012.2215612).
12. 12)
  - 7. Kamibaba, R., Takahama, K., Omura, I.: ‘Design of trench termination for high voltage devices’. 2010 22nd Int. Symp. Power Semiconductor Devices IC's (ISPSD), Hiroshima, Japan, June 2010, pp. 107–110.
13. 13)
  - 1. Kosier, S.L., Wei, A., Yau, K.C., et al: ‘Combination field plate/field ring termination structures for integrated power devices’, Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs, Monterey, CA, USA, May 2002, pp. 182–187.

Uniform shallow trenches termination design for high-voltage VDMOS transistor

References

Related content