access icon free Phase-interpolator-based glitch-free fractional frequency divider with track-and-hold technique

© The Institution of Engineering and Technology
Received 23/05/2019, Published 25/06/2019

This Letter presents an 8-bit fractional frequency divider by utilising current-mode phase interpolator (PI) for digital phase-locked loops. A novel track-and-hold circuitry is proposed between the PI and divide-by-2. It can remove the glitches generated by the current-interpolation structure. This method also relaxes the requirement of the minimum input frequency, while maintaining the same output frequency. The proposed fractional frequency divider is designed and fabricated with a 65-nm CMOS technology. It dissipates a DC power of 0.8 mW from a 1.2 V supply. The measurement result shows that the fractional frequency divider achieves an uncalibrated in-band spur of −43 dBc.

Inspec keywords: sample and hold circuits; integrated circuit design; CMOS integrated circuits; digital phase locked loops; interpolation; frequency dividers

Other keywords: digital phase-locked loops; current-interpolation structure; track-and-hold technique; voltage 1.2 V; fractional frequency divider; size 65 nm; current-mode phase interpolator; track-and-hold circuitry; CMOS technology; output frequency; minimum input frequency; phase-interpolator-based glitch-free fractional frequency divider; power 0.8 mW

Subjects: Convertors; Semiconductor integrated circuit design, layout, modelling and testing; Interpolation and function approximation (numerical analysis); Other digital circuits; Modulators, demodulators, discriminators and mixers; CMOS integrated circuits

References

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      • 4. Chandrashekar, K., Pellerano, S., Madoglio, P., et al: ‘A 32 nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management’. Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, USA, February 2012, pp. 352–353.
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      • 2. Lin, J., Jiang, H., Chi, B.: ‘A 5-bit phase-interpolator-based fractional-N frequency divider for digital phase-locked loops’. Proc. IEEE ISCAS, Baltimore, MD, USA, May 2017, pp. 1–14.
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