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access icon openaccess Oscillator without a combinatorial loop and its threat to FPGA in data centre

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      • 3. Trimberger, S., McNeil, S.: ‘Security of FPGAs in data centers’. 2017 IEEE 2nd Int. Verification and Security Workshop (IVSW), Thessaloniki, 2017, pp. 117122.
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      • 4. Giechaskiel, I., Rasmussen, K.B., Eguro, K.: ‘Leaky wires: information leakage and covert communication between FPGA long wires’. The 13rd ACM ASIA Conf. on Computer and Communications Security (ACM ASIACCS 2018), Incheon, Korea, June 2018, pp. 1527.
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      • 5. Schellenberg, F., Gnad, D.R.E., Moradi, A., et al: ‘An inside job: remote power analysis attacks on FPGAs’. 2018 Design, Automation & Test in Europe Conf. (DATE 2018), Dresden, Germany, March 2018.
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      • 6. Krautter, J., Gnad, D.R.E., Tahoori, M.B.: ‘FPGAhammer: remote voltage fault attacks on shared FPGAs, suitable for DFA on AES’, IACR Trans. Cryptographic Hardware Embedded Syst., 2018, 2018, (3), pp. 4468.
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      • 7. Xilinx: UltraScale Architecture Libraries Guide', 2014, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug974-vivado-ultrascale-libraries.pdf.
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      • 8. Xilinx: SDAccel Environment User Guide (UG1023)', 2017, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1023-sdaccel-user-guide.pdf.
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