© The Institution of Engineering and Technology
A vertically symmetric lumped element directional coupler (VSLEDC) providing broadband characteristics is proposed. In simulations, the proposed VSLEDC showed a 43.8% broader bandwidth than a horizontally and vertically symmetric lumped element directional coupler under similar design conditions for the same insertion loss. The proposed coupler was implemented in a Global Foundry 130 nm CMOS technology. The overall chip size was 1300 µm × 850 µm. The coupling was designed to be −10 dB at 1 GHz. The S-parameter measurements showed an absolute bandwidth and a fractional bandwidth of 141.1 MHz and 14.11%, respectively. Within the bandwidth, the insertion loss was 1.6‒1.8 dB.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2018.6923
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content/journals/10.1049/el.2018.6923
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Vertically symmetric broadband lumped element CMOS directional coupler