Comparator hysteresis compensation for decision feedback equalisers

Comparator hysteresis compensation for decision feedback equalisers

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High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations.


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      • 3. Mattia, O.E., Guermandi, D., Torfs, G., et al: ‘An up to 36 Gbps 5-tap 16QAM DFE for mmWave wireless communication in 28 nm CMOS’. IEEE Custom Integrated Circuits Conf. (CICC), Austin, TX, USA, April 2017, pp. 14, doi: 10.1109/CICC.2017.7993666.

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