© The Institution of Engineering and Technology
An ultra-low-voltage two-stage dynamic comparator is proposed with a forward body bias (FBB) scheme for successive approximation register (SAR) analogue-to-digital converters (ADCs). The proposed FBB scheme for a preamplifier and latch stage reduces the delay time remarkably under a low supply voltage. At 0.4 V, the power consumption is 4.48 nW, and the delay can be decreased to 593.9 ns for ΔV in = 0.1 mV and f clk = 100 kHz. The RMS equivalent input-referred noise of the comparator is 0.136 mV. The total offset is 13.7 mV, and offset fluctuation is 0.183 mV with the proposed structure. Both the input-referred noise and offset fluctuation are <0.5 least-significant bit for a 10-bit SAR ADC at 0.4 V.
References
-
-
1)
-
8. Chiu, P.-F., Zimmer, B., Nikolić, B.: ‘A double-tail sense amplifier for low-voltage SRAM in 28 nm technology’. IEEE Asian Solid-State Circuits Conf., Toyama, Japan, November 2016, pp. 181–184.
-
2)
-
2. Liu, C.-C., Chang, S.-J., Huang, G.-Y., Lin, Y.-Z.: ‘A 10 bit 50 MS/s SAR ADC with a monotonic capacitor switching procedure’, IEEE J. Solid-State Circuits, 2010, 34, pp. 731–740 (doi: 10.1109/JSSC.2010.2042254).
-
3)
-
2. Zhao, J., Mei, N., Zhang, Z., et al: ‘Vaq-based tri-level switching scheme for SAR ADC’, Electron. Lett., 2018, 54, (2), pp. 66–68 (doi: 10.1049/el.2017.3711).
-
4)
-
5. Xin, X., Cai, J., Xie, R., et al: ‘Ultra-low power comparator with dynamic offset cancellation for SAR ADC’, Electron. Lett., 2017, 53, (24), pp. 1572–1574 (doi: 10.1049/el.2017.2916).
-
5)
-
7. Elzakker, M., Tuijl, E., Geraedts, P., et al: ‘A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS/s’, J. Solid-State Circuits, 2010, 45, (5), pp. 1007–1015 (doi: 10.1109/JSSC.2010.2043893).
-
6)
-
6. Zhu, Z., Xiao, Y., Song, X.: ‘Vcm-based monotonic capacitor switching scheme for SAR ADC’, Electron. Lett., 2013, 49, (5), pp. 327–329 (doi: 10.1049/el.2012.3332).
-
7)
-
1. Carrillo, J.M., Torelli, G., Perez-Aloe, R., Duque-Carrillo, J.F.: ‘1-V rail-to-rail CMOS opamp with improved bulk-driven input stage’, IEEE J. Solid-State Circuits, 2007, 42, (3), pp. 508–517 (doi: 10.1109/JSSC.2006.891717).
-
8)
-
9. Hariprasath, V., Guerber, J., Lee, S.-H., Moon, U.-K.: ‘Merged capacitor switching based SAR ADC with highest switching energy-efficiency’, Electron. Lett., 2010, 46, (9), pp. 620–621 (doi: 10.1049/el.2010.0706).
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2018.6340
Related content
content/journals/10.1049/el.2018.6340
pub_keyword,iet_inspecKeyword,pub_concept
6
6