Ultra-low-voltage low-power dynamic comparator with forward body bias scheme for SAR ADC

Ultra-low-voltage low-power dynamic comparator with forward body bias scheme for SAR ADC

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An ultra-low-voltage two-stage dynamic comparator is proposed with a forward body bias (FBB) scheme for successive approximation register (SAR) analogue-to-digital converters (ADCs). The proposed FBB scheme for a preamplifier and latch stage reduces the delay time remarkably under a low supply voltage. At 0.4 V, the power consumption is 4.48 nW, and the delay can be decreased to 593.9 ns for ΔV in = 0.1 mV and f clk = 100 kHz. The RMS equivalent input-referred noise of the comparator is 0.136 mV. The total offset is 13.7 mV, and offset fluctuation is 0.183 mV with the proposed structure. Both the input-referred noise and offset fluctuation are <0.5 least-significant bit for a 10-bit SAR ADC at 0.4 V.


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      • 8. Chiu, P.-F., Zimmer, B., Nikolić, B.: ‘A double-tail sense amplifier for low-voltage SRAM in 28 nm technology’. IEEE Asian Solid-State Circuits Conf., Toyama, Japan, November 2016, pp. 181184.

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