Two-stage ADC-based ROICs for 25 μm-pitch cryogenic infrared focal plane array

Two-stage ADC-based ROICs for 25 μm-pitch cryogenic infrared focal plane array

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A low-power, high-linearity, high-charge handling capability two-stage ADC-based 384 × 288 size digital readout integrated circuits (ROIC) for infrared focal plane arrays are presented. A novel high-speed, low-power-consumption comparator structure is proposed in this work. Moreover, the two-stage ADC combines the pulse frequency modulation (PFM)-based pixel-level ADC and fine quantify module, improving the charge handling capability and the linearity of the readout circuit. The ROIC with 25 μm pixel pitch has been realised in 0.18 μm 1P6M CMOS process. The power consumption of the two-stage ADC is 50 μW. The charge handling capability of the pixel is 2.3 Ge and the non-linearity of the proposed circuit is 0.09%.

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