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Single-ended voltage-mode duobinary transmitter with feedback time reduced parallel precoder

Single-ended voltage-mode duobinary transmitter with feedback time reduced parallel precoder

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A duobinary transmitter (TX) is presented in a single-ended topology using voltage-mode drivers to support dynamic random access memory (DRAM) interface. A four-phase parallel duobinary precoder is included. It relaxes one of the critical timing requirements of the duobinary TX by reducing the feedback step of the precoder and performing its feedback at once. Fabricated in a 55 nm CMOS process, the TX occupies 0.053 mm2 active area. The TX achieves 10 Gbps operation at 6.8 pJ/b of energy efficiency and operates up to 12.8 Gbps at 7.6 pJ/b.

References

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      • 3. JEDEC standard: ‘Low power double data rate 4 (LPDDR4)’. Available at https://www.jedec.org/system/files/docs/JESD209-4B.pdf, last accessed February 2017.
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      • 4. Ying, Y. M., Lee, I. T., Liu, S. I.: ‘A 20 Gb/s adaptive duobinary transceiver’. Asian Solid State Circuits Conf. (A-SSCC), Kobe, Japan, November 2012, pp. 129132, doi: 10.1109/IPEC.2012.6522642.
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      • 6. Min, B., Palermo, S.: ‘A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter’. Int. Midwest Symp. Circuits and Systems (MWSCAS), Seoul, Korea, August 2011, pp. 14, doi: 10.1109/MWSCAS.2011.6026281.
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