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Hardware-efficient slope-error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver

Hardware-efficient slope-error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver

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A hardware-efficient slope-error (SE) algorithm based four-level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC-768 JTOL mask by at least 0.35 UI at the bit error rate of 10−12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm2.

References

    1. 1)
      • 1. Spagna, F., Chen, L., Deshpande, M., et al: ‘A 78 mW 11.8 Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32 nm CMOS’. ISSCC Digest of Technical Papers, San Francisco, USA, February 2010, pp. 366367.
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      • 3. Dokania, R., Kern, A., He, M., et al: ‘A 5.9pJ/b 10 Gb/s serial link with unequalised MM-CDR in 14 nm tri-gate CMOS’. ISSCC Digest of Technical Papers, San Francisco, USA, February 2015, pp. 184185.
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      • 5. Peng, P.-J., Li, J.-F., Chen, L.-Y., et al: ‘A 56 Gb/s PAM-4/NRZ transceiver in 40 nm CMOS’. ISSCC Digest of Technical Papers, San Francisco, USA, February 2017, pp. 110111.
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