Highly linear combining CMOS PA with AAAC

Highly linear combining CMOS PA with AAAC

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A highly linear and efficient CMOS power amplifier (PA) with adaptive auxiliary amplifier control (AAAC) is presented, which makes the common-gate transistor of an auxiliary amplifier operate in the saturation region for overall output powers. This leads to decrease the AM–PM distortion by reducing the variation of the output susceptance. In addition, the AAAC reduces the current consumption for all power ranges by controlling the auxiliary amplifier. The PA is fully integrated with all matching networks in a 0.18 μm CMOS process. It was measured with an 802.11n 64-QAM MCS7 signal. It achieved a maximum average power of 19.9 dBm with a power-added efficiency of 28% under an error-vector magnitude of −25 dB.


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