185–220 GHz wideband amplifier in 40 nm CMOS

185–220 GHz wideband amplifier in 40 nm CMOS

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A 185–220 GHz four-stage differential wideband amplifier is presented. The bandwidth (BW) is significantly expended by using the coupled transmission line (CTL) technique and the staggered inter-stage wideband matching technique. CTL is adopted due to its high self-resonant frequency, high simulation accuracy, compact layout and wide BW characteristics. The amplifier achieves a peak gain of 10.1 and 3 dB BW of 35 GHz ranging from 185 to 220 GHz. With a supply voltage of 0.9 V, the amplifier consumes a DC power of 54.5 mW. The amplifier occupies a core area of 500 × 250 μm2 in 40 nm CMOS.


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      • 4. Hara, S., Katayama, K., Takano, K., et al: ‘Compact 160 GHz amplifier with 15 dB peak gain and 41-GHz 3 dB bandwidth’. 2015 IEEE Radio Frequency Integrated Circuits Symp. (RFIC), Phoenix, AZ, USA, May 2015, pp. 710.
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      • 5. Park, D.W., Utomo, D.R., Hong, J.P., et al: ‘A 230–260 GHz wideband amplifier in 65 nm CMOS based on dual-peak Gmax core’. 2017 Symp. VLSI Circuits, Kyoto, Japan, June 2017, pp. C300C301.

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