FPGA implementation of adaptive digital pre-distorter with improving accuracy of lookup table by Taylor series method

FPGA implementation of adaptive digital pre-distorter with improving accuracy of lookup table by Taylor series method

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Due to the non-linear behaviour of the power amplifier (PA), the amplification of signals with fluctuating envelopes leads to distortion inevitably. These non-linear effects can be counteracted by the digital pre-distortion (DPD) with the adaption and updating of lookup table (LUT). In this Letter, a low-complexity LUT implemented by FPGA of pre-distortion PA lineariser is proposed to obtain more accurate linearisation. The algorithm utilises interpolation of the LUT with the method of Taylor series. The experiment shows that this method can be used to obtain the more accurate indexed value of LUT to estimate the PA behaviour for effective DPD.


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