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Autonomous high-speed serial link power management depending on required link performance for HMC

Autonomous high-speed serial link power management depending on required link performance for HMC

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Many studies on 3D-stacked dynamic RAMs (DRAMs) have been conducted to overcome the shortcomings of conventional DRAM. The hybrid memory cube (HMC) is one of the most promising 3D-stacked DRAMs, thanks to its high bandwidth and expandable structure. However, a high-speed serial link that interfaces the CPU and HMC consumes significant power, primarily because of the high overhead incurred in synchronising its clock. Although the link provides low-power modes, managing them is very difficult because of their long mode transition times. An autonomous power management method for the high-speed link is proposed. The proposed method determines the optimal number of active links while satisfying the required link performance. Simulations demonstrate that the proposed method reduces link power consumption by an average of 63.06% with a performance degradation of only 1.36%. Therefore, this proposed autonomous link power management is an outstanding option for low-power HMC-based systems.

References

    1. 1)
      • 1. Ahn, J., Hong, S., Choi, K.: ‘Dynamic power management of off-chip links for hybrid memory cubes’. Design Automation Conf. (DAC), San Francisco, USA, June 2014.
    2. 2)
      • 2. Hybrid Memory Cube Consortium (HMCC): ‘Hybrid Memory Cube Specification 2.1’.
    3. 3)
      • 3. Kroft, D.: ‘Lockup-free instruction fetch/prefetch cache organization’. Int. Symp. Computer Architecture (ISCA), Minneapolis, USA, May 1981.
    4. 4)
    5. 5)
    6. 6)
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