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1887

access icon free 0.5–4.4 Gbit/s PAM4/NRZ dual-mode transceiver with 0.6 V near-ground NMOS driver for low-power memory interface

  • Author(s): K. Min 1  and  T. Oh 1
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  • Source: Volume 54, Issue 11, 31 May 2018, p. 684 – 685
    DOI:  10.1049/el.2018.0871 , Print ISSN 0013-5194, Online ISSN 1350-911X
© The Institution of Engineering and Technology
Received 13/03/2018, Published 27/04/2018

An efficient dual-mode input and output transceiver scheme is proposed. The transceiver can achieve the data speed from 0.5 up to 4.4 Gbit/s with 0.6 V supply voltage and can support the near-ground mode for low-power memory interface application. The transceiver can transmit both PAM4/NRZ signals flexibly depending on the channel loss conditions. The prototype bi-directional two-channel transceiver is implemented in 45 nm CMOS process and occupies 0.0516 mm2 chip area. The IP shows power consumption of 2.24/2.78 mW during 4.4 Gbit/s PAM4/NRZ mode operation, each, respectively.

Inspec keywords: low-power electronics; driver circuits; CMOS memory circuits; transceivers

Other keywords: low-power memory interface application; channel loss condition; size 45 nm; voltage 0.6 V; power 2.24 mW; bidirectional two channel transceiver; CMOS process; bit rate 0.5 Gbit/s to 4.4 Gbit/s; near-ground NMOS driver; near-ground mode; power 2.78 mW; PAM4-NRZ dual-mode input-output transceiver scheme

Subjects: CMOS integrated circuits; Semiconductor storage; Power electronics, supply and supervisory circuits; Memory circuits

References

    1. 1)
      • 2. Choi, W.-S., Shu, G., Talegaonkar, M., et al: ‘A 0.45-to-0.7 V 1-to-6 Gb/s 0.29-to-0.58 pJ/b source-synchronous transceiver using automatic phase calibration in 65 nm CMOS’. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, February 2015, pp. 66–67, doi: 10.1109/ISSCC.2015.7062928.
    2. 2)
      • 3. Bae, W., Yoo, B.-J., Jeong, D.-K.: ‘Design of CMOS 5 Gb/s 4-PAM transceiver front-end for low-power memory interface’. IEEEInt. SoC Design Conf., Jeju Island, South Korea, November 2012, pp. 49–51, doi: 10.1109/ISOCC.2012.6406922.
    3. 3)
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