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0.5–4.4 Gbit/s PAM4/NRZ dual-mode transceiver with 0.6 V near-ground NMOS driver for low-power memory interface

0.5–4.4 Gbit/s PAM4/NRZ dual-mode transceiver with 0.6 V near-ground NMOS driver for low-power memory interface

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An efficient dual-mode input and output transceiver scheme is proposed. The transceiver can achieve the data speed from 0.5 up to 4.4 Gbit/s with 0.6 V supply voltage and can support the near-ground mode for low-power memory interface application. The transceiver can transmit both PAM4/NRZ signals flexibly depending on the channel loss conditions. The prototype bi-directional two-channel transceiver is implemented in 45 nm CMOS process and occupies 0.0516 mm2 chip area. The IP shows power consumption of 2.24/2.78 mW during 4.4 Gbit/s PAM4/NRZ mode operation, each, respectively.

References

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    2. 2)
      • 2. Choi, W.-S., Shu, G., Talegaonkar, M., et al: ‘A 0.45-to-0.7 V 1-to-6 Gb/s 0.29-to-0.58 pJ/b source-synchronous transceiver using automatic phase calibration in 65 nm CMOS’. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, February 2015, pp. 6667, doi: 10.1109/ISSCC.2015.7062928.
    3. 3)
      • 3. Bae, W., Yoo, B.-J., Jeong, D.-K.: ‘Design of CMOS 5 Gb/s 4-PAM transceiver front-end for low-power memory interface’. IEEEInt. SoC Design Conf., Jeju Island, South Korea, November 2012, pp. 4951, doi: 10.1109/ISOCC.2012.6406922.
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