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Calibrated 10 b 28 nm CMOS SAR ADC based on integer-based split capacitors

Calibrated 10 b 28 nm CMOS SAR ADC based on integer-based split capacitors

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A calibrated 10 b 5 MS/s 28 nm CMOS successive-approximation-register ADC based on an integer-based split capacitor array is presented. The proposed ADC employs a split capacitor array to optimise the overall power consumption, chip area and linearity performance. An attenuation capacitor between two capacitor arrays is implemented with an integer multiple of unit capacitors rather than a fraction of unit capacitors. The proposed calibration of capacitors reduces the non-linearity error caused by device mismatches in the conventional split capacitor array. The measured prototype ADC which has an active die area of 0.063 mm2 shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 59.25 and 70.44 dB, respectively, and consumes 42.5 μW at 0.7 V and 5 MS/s. Moreover, the measured differential non-linearity (NL) and integral NL are within 0.36 and 0.52 least significant bit, respectively, after calibration.

References

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      • 2. Jeong, J.M., An, T.J., Shin, H.W., et al: ‘A 0.16 mm2 12 b 30 MS/s 0.18 μm CMOS SAR ADC based on low-power composite switching’. IEEE Int. SoC Design Conf., Gyungju, South Korea, November 2015, pp. 7980, doi: 10.1109/ISOCC.2015.7401641.
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