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Low-complexity, high-speed multi-size cyclic-shifter for quasi-cyclic LDPC decoder

Low-complexity, high-speed multi-size cyclic-shifter for quasi-cyclic LDPC decoder

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Quasi-cyclic low-density parity check (QC-LDPC) codes are being widely used in communication standards, and the decoder of QC-LDPC codes requires a unique type of rotator. The unique rotator, called a multi-size cyclic-shifter (MSCS), should be able to rotate data with various sizes, and many structures have been proposed for the operation. A low-complexity, high-speed MSCS structure is proposed, in which a part of the previous smallest structure is replaced with a structure with less delay and comparable area. The synthesis results present that the proposed structure achieves not only the highest speed but also the lowest complexity after synthesis.

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      • 5. Peng, X., Chen, Z., Zhao, X., et al: ‘A 115 mW 1 Gbps QC-LDPC decoder ASIC for WiMAX in 65 nm CMOS’. Proc. IEEE Asian Solid-State Circuits Conf., 2011, pp. 317320.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.4456
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