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Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process

Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process

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The effect of optimising the transistor finger width on the performance of high-speed analogue circuits in deep sub-micron processes is investigated, demonstrated in a 28 nm high-K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used.

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.4453
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