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access icon free Power optimisation of both a high-speed counter and a retiming element for 2.4 GHz digital PLLs

The power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal.

References

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      • 3. Chillara, V.K., Liu, Y., Wang, B., et al: ‘An 860 μW 2.1-to-2.7 GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (bluetooth smart and ZigBee) applications’. IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, USA, February 2014, pp. 172173.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.4391
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content/journals/10.1049/el.2017.4391
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