160 MS/s 20 MHz bandwidth third-order noise shaping SAR ADC

160 MS/s 20 MHz bandwidth third-order noise shaping SAR ADC

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This Letter proposes an operational-amplifier free with an embedded passive gain technique to implement an oversampling, noise shaping successive approximation register (SAR) ADCs. In the proposed scheme, the comparator noise, quantisation noise, settling errors and DAC thermal noise are alleviated. A third-order noise shaping SAR ADC with inserted passive gain design in 40 nm CMOS technology is well suited for low power application because of using passive elements like capacitors and switches. Due to the oversampling and shaping scheme, the structure can be used for high-speed and high-resolution operation.


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      • 2. Chen, Z., Miyahara, M., Matsuzawa, A.: ‘A 9.35-ENOB, 14.8fJ/conv.-step fully-passive noise-shaping SAR ADC’. IEEE Symp. on Very Large Scale Integration Circuits (VLSI Circuits), Kyoto, Japan, 2015, pp. C64C65, doi: 10.1109/VLSIC.2015.7231329.
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      • 3. Chen, Zh, Miyahara, M., Matsuzawa, A.: ‘A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain’. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Toyama, Japan, 2016, pp. 309312, doi: 10.1109/ASSCC.2016.7844197.
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