Controlling fixed trap charge effect in FinFET using heterodielectric BOX

Controlling fixed trap charge effect in FinFET using heterodielectric BOX

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This Letter presents an Si FinFET on heterodielectric BOX, where the effect of trap charges can be avoided. The investigation is based on a 3D simulation study. The BOX height also plays a significant role in the device characteristics. The effect of trap charges using homodielectric and heterodielectric BOX is verified by plotting the electron density across a 2D cross section in the middle of the channel. The authors further investigated the effect of temperatures, ranging from room temperature to higher temperatures. The FinFET, with heterodielectric BOX, shows no trap effect even when the temperature is varied. On the other hand, a visible temperature effect is observed in case of homodielectric BOX. Moreover, in case of homodielectric BOX, the ON–OFF performance metric, (Q) is affected in presence of trap charges; whereas no change is observed when a heterodielectric BOX is used. As such, it is found that the FinFET with heterodielectric BOX is more reliable and useful for current semiconductor industries.


    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
      • 5. Cheng, H-W., Li, F.-H., Han, M.-H., et al: ‘3D device simulation of work function and interface trap fluctuations on high-κ/metal gate devices’, Int. Electron Devices Meeting (IEDM), San Francisco, CA, 2010, pp., doi: 10.1109/IEDM.2010.5703370.
    6. 6)
      • 6. Ramos, J., Augendre, E., Kottantharayil, A., et al: ‘Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs’. 8th Int. Conf. Solid-State and Integrated Circuit Technology Proc., Shanghai, 2006, pp. 7274, doi: 10.1109/ICSICT.2006.306080.
    7. 7)
      • 7. Franco, J., Kaczer, B., Roussel, Ph.J., et al: ‘Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO2/HfO2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks’. Int. Electron Devices Meeting (IEDM), Washington, DC, 2013, pp., doi: 10.1109/IEDM.2013.6724634.
    8. 8)
    9. 9)
      • 9. Sentaurus Device User, Synopsys, 2009, p. 2009.
    10. 10)
    11. 11)

Related content

This is a required field
Please enter a valid email address