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An area-efficient tri-level switching scheme is proposed for the successive approximation register (SAR) analogue-to-digital converters (ADCs). Unlike existing tri-level scheme, the proposed switching scheme is based on a new third reference voltage V aq which is a quarter of the reference voltage V ref. With reusing the least significant bit capacitors in the last two bits generation, the proposed switching scheme achieves 87.5% less number of unit capacitors and 96.48% less switching energy over the conventional scheme.
References
-
-
1)
-
5. Xie, L., Su, J., Liu, J., Wen, G.: ‘Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs’, Electron. Lett., 2015, 51, (6), pp. 466–467 (doi: 10.1049/el.2015.0008).
-
2)
-
2. Liu, C.-C., Chang, S.-J., Huang, G.-Y., Lin, Y.-Z.: ‘A 10 bit 50 MS/s SAR ADC with a monotonic capacitor switching procedure’, IEEE J. Solid-State Circuits, 2010, 34, pp. 731–740 (doi: 10.1109/JSSC.2010.2042254).
-
3)
-
25. Zhu, Y., Chan, Ch., Chio, U., et al: ‘A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS’, IEEE J. Solid-State Circuits, 2010, 45, (6), pp. 1111–1121 (doi: 10.1109/JSSC.2010.2048498).
-
4)
-
5. Yuan, C., Lam, Y.: ‘Low-energy and area-efficient tri-level switching scheme for SAR ADC’, Electron. Lett., 2012, 48, (9), pp. 482–483 (doi: 10.1049/el.2011.4001).
-
5)
-
4. Rahimi, E., Yavari, M.: ‘Energy-efficient high-accuracy switching method for SAR ADCs’, Electron. Lett., 2014, 50, (6), pp. 499–501 (doi: 10.1049/el.2013.3451).
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.3711
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V aq-based tri-level switching scheme for SAR ADC