© The Institution of Engineering and Technology
This Letter proposes an on-chip data strobe transmission circuit for dynamic random access memory (DRAM). The on-chip differential repeaters with cross-coupled latches are adopted to prevent the sampling margin reduction. A node monitoring circuit has been proposed to prevent short-circuit currents of the on-chip differential repeaters and cross-coupled latches caused by high impedance inputs. When compared with the conventional differential signalling, the proposed circuit can save the short-circuit current of 6.2 mA per a single write operation. The chip has been fabricated in 350 nm CMOS technology and the active chip area is 0.189 mm2.
References
-
-
1)
-
2. Lee, S.M., Oh, J., Choi, J., et al: ‘A 0.6V 4.266 Gb/s/pin LPDDR4X interface with autoDQS cleaning and write-VWM training for memory controller’. IEEE Int. Solid State Circuits Conf. – Digest of Technical Papers, San Francisco, February 2017, pp. 398–399, .
-
2)
-
3. Qiu, Y., Zeng, Y., Zhang, F.: ‘1–5 GHz duty-cycle corrector circuit with wide correction range and high precision’, Electron. Lett., 2014, 50, (11), pp. 792–794 (doi: 10.1049/el.2014.0170).
-
3)
-
4. Garlepp, B.W., Donnelly, K.S., Kim, J., et al: ‘A portable digital DLL for high-speed CMOS interface circuits’, J. Solid-State Circuits, 1999, 34, (5), pp. 632–644 (doi: 10.1109/4.760373).
-
4)
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