access icon free On-chip data strobe transmission with short-circuit current protection scheme for dynamic random access memory

© The Institution of Engineering and Technology
Received 25/09/2017, Published 24/11/2017

This Letter proposes an on-chip data strobe transmission circuit for dynamic random access memory (DRAM). The on-chip differential repeaters with cross-coupled latches are adopted to prevent the sampling margin reduction. A node monitoring circuit has been proposed to prevent short-circuit currents of the on-chip differential repeaters and cross-coupled latches caused by high impedance inputs. When compared with the conventional differential signalling, the proposed circuit can save the short-circuit current of 6.2 mA per a single write operation. The chip has been fabricated in 350 nm CMOS technology and the active chip area is 0.189 mm2.

Inspec keywords: flip-flops; short-circuit currents; DRAM chips; CMOS memory circuits

Other keywords: DRAM; cross-coupled latches; CMOS technology; active chip area; current 6.2 mA; single-write operation; size 350 nm; on-chip differential repeaters; sampling margin reduction; high-impedance inputs; short-circuit current protection scheme; differential signalling; node monitoring circuit; on-chip data strobe transmission circuit

Subjects: Semiconductor storage; Logic circuits; CMOS integrated circuits; Memory circuits; Logic and switching circuits

References

    1. 1)
      • 2. Lee, S.M., Oh, J., Choi, J., et al: ‘A 0.6V 4.266 Gb/s/pin LPDDR4X interface with autoDQS cleaning and write-VWM training for memory controller’. IEEE Int. Solid State Circuits Conf. – Digest of Technical Papers, San Francisco, February 2017, pp. 398–399, doi: 10.1109/ISSCC.2017.7870429.
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    4. 4)
      • 1. JEDEC Standard: ‘LPDDR4 SDRAM specification, JESD209-4’. August 2014.
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