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On-chip data strobe transmission with short-circuit current protection scheme for dynamic random access memory

On-chip data strobe transmission with short-circuit current protection scheme for dynamic random access memory

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This Letter proposes an on-chip data strobe transmission circuit for dynamic random access memory (DRAM). The on-chip differential repeaters with cross-coupled latches are adopted to prevent the sampling margin reduction. A node monitoring circuit has been proposed to prevent short-circuit currents of the on-chip differential repeaters and cross-coupled latches caused by high impedance inputs. When compared with the conventional differential signalling, the proposed circuit can save the short-circuit current of 6.2 mA per a single write operation. The chip has been fabricated in 350 nm CMOS technology and the active chip area is 0.189 mm2.

References

    1. 1)
      • 1. JEDEC Standard: ‘LPDDR4 SDRAM specification, JESD209-4’. August 2014.
    2. 2)
      • 2. Lee, S.M., Oh, J., Choi, J., et al: ‘A 0.6V 4.266 Gb/s/pin LPDDR4X interface with autoDQS cleaning and write-VWM training for memory controller’. IEEE Int. Solid State Circuits Conf. – Digest of Technical Papers, San Francisco, February 2017, pp. 398399, doi: 10.1109/ISSCC.2017.7870429.
    3. 3)
    4. 4)
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.3634
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