In-DRAM bitwise processing circuit for low-power and fast computation

In-DRAM bitwise processing circuit for low-power and fast computation

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In-DRAM processing circuit is able to reduce operation time and power consumption than the traditional CPU + MEMORY system in performing the complicated computation such as convolution. These benefits are gained by bitwise and parallel processing of the in-DRAM convolution circuit. To realise the in-DRAM circuit, an inter-bank processing circuit is proposed with bitwise summation/comparison circuit for performing convolution inside DRAM. Compared to the intra-bank bitwise operation, the inter-bank circuit can significantly reduce the power consumption and the number of row activation cycles to accomplish convolution. For the number of cycles, the inter-bank circuit takes only 65 cycles for calculating 16 × 16 feature map. On the contrary, the intra-bank needs as many as 192 cycles. In terms of power consumption, the inter-bank circuit consumes smaller power by 35% than the intra-bank. In the proposed in-DRAM processing circuit, no complicated multiplier and adder are needed in performing the convolution. The Modified National Institute of Standards and Technology (MNIST) recognition rate of the proposed bitwise processing circuit can be as high as 97.28%, indicating very little loss due to the ternary kernels.


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      • 1. Seshadri, V., Kim, Y., Fallin, C., et al: ‘Rowclone: fast and energy-efficient in-DRAM bulk data copy and initialization’. 2013 46th Annual IEEE/ACM Int. Symp. Microarchitecture (MICRO), USA, 2013.
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