Your browser does not support JavaScript!

access icon free Logic operation-based Design for Testability method and parallel test algorithm for 1T1R crossbar

Among resistive random access memory (RRAM) architectures, one transistor one memristor (1T1R) crossbar is the most fledged one. For 1T1R crossbar, a logic operation-based Design for Testability and parallel test algorithm, which is an improvement of March C*-1T1R test algorithm, are proposed. The pass-fail fault dictionary of the proposed test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors and traditional RAM. Compared with March MOM, March C* and March C*-1T1R, the test time of the proposed test algorithm is reduced with a little area overhead for a large size crossbar.


    1. 1)
    2. 2)
      • 6. Chen, C.Y., Li, J.F.: ‘Fault modeling and testing of 1T1R memristor memories’. IEEE VLSI Test Symp., 2015, p. 1.
    3. 3)
    4. 4)
    5. 5)
    6. 6)

Related content

This is a required field
Please enter a valid email address