Self-biased CMOS LC VCO based on trans-conductance linearisation technique
Introduction: A self-biased low-phase noise CMOS LC VCO (employing both nMOS and pMOS switching transistors) based on the trans-conductance linearisation of active devices is proposed. The self-biased push–pull configuration with resistors between the LC tank and device drain, not only reduces power consumption, but also is capable of removing the RF choking inductor needed in NMOS-only or PMOS-only topology, which results into a compact chip area. A capacitive-coupled feedback from the drain and LC tank improves the oscillation amplitude and reduces the tank loading. The proposed VCO is fabricated and measured with a 65 nm CMOS process. The core chip area is 0.12 mm2. The measured oscillation frequency ranges from 3.96 to 6.1 GHz, the phase noise at 1 MHz offset is from −123 to −125 dBc/Hz, with a power dissipation from 13 to 23 mW under a 1.3 V supply voltage across the frequency tuning range. The achieved figure-of-merit with tuning range (FoMT) from 196.5 to 199.5 dBc/Hz.
