© The Institution of Engineering and Technology
This Letter proposes a new scheme to eliminate the bit-line leakage current of static random access memory. The proposed scheme utilises a four-input sense amplifier to amplify the voltages of self-compared bit-line pairs. The bit-lines of the proposed structure have no series capacitances and are directly connected to the sense amplifier input. By this way, read delay and error caused by the leakage current of bit-lines will be eliminated. Simulation results in SMIC 28 nm CMOS process design kits show that the proposed scheme has better stability and can decrease delay time by 41.1% at 0.9 V supply voltage compared with the X-Calibration technology.
References
-
-
1)
-
5. Natarajan, A., Shankar, V., Maheshwari, A., et al: ‘Sensing design issues in deep submicron CMOS SRAMs’. IEEE Computer Society Symp. VLSI: New Frontiers in VLSI Design, Tampa, FL, USA, May 2005, pp. 42–45.
-
2)
-
4. Agawa, K., Hara, , H., Takayanagi, T., et al: ‘A bitline leakage compensation scheme for low-voltage SRAMs’, J. Solid-State Circuits, 2001, 36, (5), pp. 726–734 (doi: 10.1109/4.918909).
-
3)
-
9. Zhiting, L., Xiulong, W., Li, Z., et al: ‘A pipeline replica bitline technique for suppressing timing variation of SRAM sense amplifiers in a 28-nm CMOS process’, J. Solid-State Circuits, 2017, 52, (3), pp. 669–677 (doi: 10.1109/JSSC.2016.2634701).
-
4)
-
2. Naeem, M., Bai-Sun, K.: ‘10T SRAM using half-VDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage’, Trans. Very Large Scale Integr. (VLSI) Syst., 2016, PP, (99), pp. 1193–1203.
-
5)
-
1. Wang, B., Nguyen, , T.Q., Do, Tuan Do, , A., et al: ‘Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement’, Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (2), pp. 441–448 (doi: 10.1109/TCSI.2014.2360760).
-
6)
-
6. Ya-Chun, L., Shi-Yu, H.: ‘X-calibration: a technique for combating excessive bitline leakage current in nanometer SRAM designs’, J. Solid-State Circuits, 2008, 43, (9), pp. 1964–1971 (doi: 10.1109/JSSC.2008.2001937).
-
7)
-
3. Goudarzi, M., Ishihara, T.: ‘SRAM leakage reduction by row/-column redundancy under random within-die delay variation’, Trans. Very Large Scale Integr. (VLSI) Syst., 2010, 18, (12), pp. 1660–1671 (doi: 10.1109/TVLSI.2009.2026048).
-
8)
-
7. TuanDo, A., Lee, Z.C., Wang, B., et al: ‘0.2 V 8T SRAM with PVT-aware bitline sensing and column-based data randomization’, J. Solid-State Circuits, 2016, 51, (6), pp. 1487–1498 (doi: 10.1109/JSSC.2016.2540799).
-
9)
-
8. Chua-Chin, W., Wang, D.-S., Liao, C.-H., et al: ‘A leakage compensation design for low supply voltage SRAM’, Trans. Very Large Scale Integr. (VLSI) Syst., 2016, 24, (5), pp. 1761–1769 (doi: 10.1109/TVLSI.2015.2484386).
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