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Self-compared bit-line pairs for eliminating effects of leakage current

Self-compared bit-line pairs for eliminating effects of leakage current

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This Letter proposes a new scheme to eliminate the bit-line leakage current of static random access memory. The proposed scheme utilises a four-input sense amplifier to amplify the voltages of self-compared bit-line pairs. The bit-lines of the proposed structure have no series capacitances and are directly connected to the sense amplifier input. By this way, read delay and error caused by the leakage current of bit-lines will be eliminated. Simulation results in SMIC 28 nm CMOS process design kits show that the proposed scheme has better stability and can decrease delay time by 41.1% at 0.9 V supply voltage compared with the X-Calibration technology.

References

    1. 1)
    2. 2)
      • 2. Naeem, M., Bai-Sun, K.: ‘10T SRAM using half-VDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage’, Trans. Very Large Scale Integr. (VLSI) Syst., 2016, PP, (99), pp. 11931203.
    3. 3)
    4. 4)
    5. 5)
      • 5. Natarajan, A., Shankar, V., Maheshwari, A., et al: ‘Sensing design issues in deep submicron CMOS SRAMs’. IEEE Computer Society Symp. VLSI: New Frontiers in VLSI Design, Tampa, FL, USA, May 2005, pp. 4245.
    6. 6)
    7. 7)
    8. 8)
    9. 9)
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