access icon free Parallel CRC architecture for broadband communication systems

Parallel cyclic redundancy check (CRC) architecture for high-throughput forward error correction decoders in broadband communication systems is proposed. Large amount of data bits are needed to be transmitted in a unit of a transport block (TB) in broadband communication systems. Owing to implementation complexity, TB is segmented into multiple small units of code blocks (CBs). The parallel CRC architecture proposed recursively calculates the TB CRC using individual CB CRCs. The proposed parallel CRC architecture is used to balance optimally between memory requirement and computational complexity.

Inspec keywords: forward error correction; cyclic redundancy check codes; broadcast communication

Other keywords: transport block; code blocks; parallel CRC architecture; parallel cyclic redundancy check architecture; CB CRC; broadband communication systems; high-throughput forward error correction decoders; TB CRC

Subjects: Codes

References

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      • 9. Sun, Y., Kim, M.S.: ‘A table-based algorithm for pipelined CRC calculation’. Proc. IEEE ICC, Cape Town, South Africa, May 2010, pp. 15.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.1029
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