access icon free Three-dimensional AND flash memory

High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 104 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

Inspec keywords: parallel memories; integrated circuit reliability; flash memories

Other keywords: 3D stacked vertical-AND array; parallel connected cell array structure; high-speed charge-trapping AND flash memory array; endurance cycle reliability; uniform program-erase characteristics; high-density charge-trapping AND flash memory array; read current drivability; three-dimensional AND flash memory; back-pattern dependency; threshold voltage window; bit-sensing speed; word-lines

Subjects: Reliability; Storage system design; Memory circuits; Semiconductor storage

References

    1. 1)
    2. 2)
      • 1. Kim, K.: ‘Silicon technologies and solutions for the data-driven world’. IEEE ISSCC Dig. Tech. Papers, 2015, pp. 814, doi: 10.1109/ISSCC.2015.7062845.
    3. 3)
    4. 4)
      • 6. Nozoe, A., Yamazaki, T., Sato, H., et al: ‘A 3.3 V high-density AND flash memory with 1 ms/512B erase & program time’. IEEE ISSCC Dig. Tech. Papers, 1995, pp. 124125, doi: 10.1109/ISSCC.1995.535458.
    5. 5)
    6. 6)
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