Power-jitter trade-off analysis in digital-to-time converters

Power-jitter trade-off analysis in digital-to-time converters

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Digital-to-time converters are one of the main building blocks in time-domain signal processing. The jitter-power product is analysed and shown to scale up linearly as the full-scale delay range in current-mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current-mode ones only when their output range is lower than about 1.4 times the clock period.


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      • 6. Gao, X., Burg, O., Wang, H., et al: ‘A 2.7-to-4.3 GHz, 0.16 ps rms-jitter, −246.8 dB-FOM, digital fractional-N sampling PLL in 28 nm CMOS’. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, CA, USA, February, 2016, pp. 174176.
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