Single-ended 2 ch. × 3.4 Gbit/s dual-mode near-ground transmitter IO driver in 45 nm CMOS process

Single-ended 2 ch. × 3.4 Gbit/s dual-mode near-ground transmitter IO driver in 45 nm CMOS process

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A smart dual-mode IO driver and termination scheme is proposed and power is efficiently consumed for both low-speed data transmission under 500 Mbit/s and high-speed data transmission up to 3.4 Gbit/s. During high speed data transmission, the driver uses near-ground signalling and pre-emphasis weight can be controlled for inter symbol interference (ISI) mitigation. The measured eye shows 17.8% vertically and 19.5% horizontally with finite impulse response (FIR) tap control for 15.75″ FR4 channel. The proto-type 2 channel single-ended driver has been implemented in 45 nm CMOS process and occupies 0.022 mm2 chip area.


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      • 1. Inti, R., Elshazly, A., Young, B., et al: ‘A highly digital 0.5-to-4 Gb/s 1.9 mW/Gb/s serial-link transceiver using current-recycling in 90 nm CMOS’. IEEE Int. Solid-State Circuits Conf., 2011, pp. 152154, doi: 10.1109/ISSCC.2011.5746260.
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