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Low power-delay-product dynamic CMOS circuit design techniques

Low power-delay-product dynamic CMOS circuit design techniques

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Two low power-delay-product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed techniques can improve circuit PDP by 19.2 and 61.9% in two non-inverted dynamic benchmarks, respectively, and 6.2 and 33.72% in two inverted dynamic benchmarks, respectively.

References

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      • 1. Xue, H.: ‘Timing and power optimization using mixed-dynamic-static CMOS’. Electronic thesis, Wright State University, 2013.
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      • 2. Baker, R., Li, H., Boyce, D.: ‘CMOS circuit design, layout, and simulation’ (John Wiley & Sons, Hoboken, NJ, 2008, 2nd edn.).
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      • 3. Weste, N., Harris, D.: ‘CMOS VLSI design’ (Pearson Education, Boston, MS, 2011, 4th edn.).
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      • 5. Meher, P., Mahapatra, K.: ‘A high speed low noise CMOS dynamic full adder cell’. Int. Conf. on Circuits, Controls & Communications (CCUBE), 2013, pp. 14.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.4173
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