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Meta-stability immunity technique for high speed SAR ADCs

Meta-stability immunity technique for high speed SAR ADCs

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An 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.

References

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      • 3. Kundu, S., Lu, J., Alpman, E., et al: ‘A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN’. Proc. of the IEEE 2014 Custom Integrated Circuits Conference, San Jose, CA, USA, September2014, pp. 14.
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